MMC2107 Datasheet, PDF (376/618 Pages) –

Freescale Semiconductor, Inc.
Serial Peripheral Interface Module (SPI)
17.7.1 SPI Control Register 1
Address: 0x00cb_0000
Bit 7
6
5
4
3
2
1
Read:
SPIE
Write:
SPE SWOM MSTR CPOL CPHA SSOE
Reset: 0
0
0
0
0
1
0
Figure 17-2. SPI Control Register 1 (SPICR1)
Bit 0
LSBFE
0
Read: Anytime
Write: Anytime
SPIE — SPI Interrupt Enable Bit
The SPIE bit enables the SPIF and MODF flags to generate interrupt
requests. Reset clears SPIE.
1 = SPIF and MODF interrupt requests enabled
0 = SPIF and MODF interrupt requests disabled
SPE — SPI System Enable Bit
The SPE bit enables the SPI and dedicates SPI port pins [3:0] to SPI
functions. When SPE is clear, the SPI system is initialized but in a
low-power disabled state. Reset clears SPE.
1 = SPI enabled
0 = SPI disabled
SWOM — SPI Wired-OR Mode Bit
The SWOM bit configures the output buffers of SPI port pins [3:0] as
open-drain outputs. SWOM controls SPI port pins [3:0] whether they
are SPI outputs or general-purpose outputs. Reset clears SWOM.
1 = Output buffers of SPI port pins [3:0] open-drain
0 = Output buffers of SPI port pins [3:0] CMOS drive
Technical Data
376
Serial Peripheral Interface Module (SPI)
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MMC2107 – Rev. 2.0
MOTOROLA