MMC2107 Datasheet, PDF (136/618 Pages) –

Freescale Semiconductor, Inc.
Reset Controller Module
5.7 Functional Description
This subsection provides a functional description of the MMC2107 reset
controller module.
5.7.1 Reset Sources
Table 5-3 defines the sources of reset and the signals driven by the reset
controller.
Table 5-3. Reset Source Summary
Source
Power on
External RESET pin (not stop mode)
External RESET pin (during stop mode)
Watchdog timer
Loss of clock
Loss of lock
Software
Type
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Asynchronous
Synchronous
To protect data integrity, a synchronous reset source is not acted upon
by the reset control logic until the end of the current bus cycle. Reset is
then asserted on the next rising edge of the system clock after the cycle
is terminated. Whenever the reset control logic must synchronize reset
to the end of the bus cycle, the internal bus monitor is automatically
enabled regardless of the BME bit setting in the chip configuration
register (CCR). Then if the current bus cycle is not terminated normally,
the bus monitor terminates the cycle based on the length of time
programmed in the BMT field of CCR.
Internal single-byte, half-word, or word writes are guaranteed to
complete without data corruption when a synchronous reset occurs.
External writes, including word writes to 16-bit ports, are also
guaranteed to complete.
Asynchronous reset sources usually indicate a catastrophic failure.
Therefore, the reset control logic does not wait for the current bus cycle
to complete. Reset is asserted immediately to the system.
Technical Data
136
Reset Controller Module
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MMC2107 – Rev. 2.0
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