MMC2107 Datasheet, PDF (190/618 Pages) –

Freescale Semiconductor, Inc.
Non-Volatile Memory FLASH (CMFR)
NOTE:
NOTE:
The address range of the shadow information is the entire address
range of the array, but the high order array addresses, are not used
to encode the location.
When SIE = 1, only the program page buffer associated with the lowest
block can be programmed. The other program page buffers cannot be
accessed and do not apply any programming voltages to their array
blocks while programming the shadow information. The shadow
information is in block 0.
LOCKCTL — Lock Control Bit
The read-always, set-once LOCKCTL bit controls the write-lock
function. Once the LOCKCTL bit is set in normal operation, the
write-lock can only be disabled again by a master reset. The
LOCKCTL bit is writable if the device is in debug mode.
1 = Write-locked registers protected
0 = Write-lock disabled
Setting the LOCKCTL bit locks the SUPV[7:0], DATA[7:0] and
PROTECT[7:0] bits. Writing to these bits has no effect; the cycle ends
normally and the bits do not change.
If LOCKCTL is set before PROTECT[7:0] is cleared, the device must use
debug mode to program or erase the CMFR.
The default reset state of LOCKCTL is 0. It can be set once after
master reset to allow protection of the write-locked register bits after
initialization.
If the LOCKCTL bit and write-locked register bits are written
simultaneously, the new value does not affect the current cycle.
DIS — Disable Bit
The read-always DIS bit disables array information. Writing to DIS has
no effect if the SES bit is set. When DIS is set, the array is disabled
and the CMFR BIU does not respond to array accesses.
The reset value is defined during reset configuration by the external
D28 pin.
1 = Array information disabled
0 = Array information enabled
Technical Data
190
Non-Volatile Memory FLASH (CMFR)
For More Information On This Product,
Go to: www.freescale.com
MMC2107 – Rev. 2.0
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