MMC2107 Datasheet, PDF (500/618 Pages) –

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Table 18-17. Error Resulting From Input Leakage (I_Off)
Source Impedance
Leakage Value (10-Bit Conversions)
100 nA
200 nA
500 nA
1000 nA
1 kΩ
—
—
0.1 counts 0.2 counts
10 kΩ
0.2 counts 0.4 counts 1 counts
2 counts
100 kΩ
2 counts
4 count
10 counts 20 counts
18.12 Interrupts
The four interrupt lines are outputs of the module and have no priority or
arbitration within the module.
18.12.1 Interrupt Operation
QADC inputs can be monitored by polling or by using interrupts. When
interrupts are not needed, software can disable the pause and
completion interrupts and monitor the completion flag and the pause flag
for each queue in the status register (QASR). In other words, flag bits
can be polled to determine when new results are available.
Table 18-18 shows the status flag and interrupt enable bits which
correspond to queue 1 and queue 2 activity.
Table 18-18. QADC Status Flags and Interrupt Sources
Queue
Queue Activity
Result written to last CCW in queue 1
Queue 1 _{Result written for a CCW with pause bit set in}
queue 1
Result written to last CCW in queue 2
Queue 2 _{Result written for a CCW with pause bit set in}
queue 2
Status Interrupt
Flag Enable Bit
CF1
CIE1
PF1
PIE1
CF2
CIE2
PF2
PIE2
If interrupts are enabled for an event, the QADC requests interrupt
service when the event occurs. Using interrupts does not require
continuously polling the status flags to see if an event has taken place.
Technical Data
500
Queued Analog-to-Digital Converter (QADC)
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MMC2107 – Rev. 2.0
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