MMC2107 Datasheet, PDF (551/618 Pages) –

MMC2107 – Rev. 2.0
MOTOROLA
Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
Boundary Scan
Table 21-3. Boundary-Scan Register Definition (Sheet 3 of 4)
(Note: Shaded regions indicate optional pins)
Bit
Logical State and Direction
Control Bits for Each Pin
94 ICOC1_0 logical state
95 ICOC1_0 direction control
96 CSE1 logical state
97 CSE1 direction control
98 R/W logical state
99 R/W direction control
100 ICOC1_1 logical state
101 ICOC1_1 direction control
102 ICOC1_2 logical state
103 ICOC1_2 direction control
104 ICOC1_3 logical state
105 ICOC1_3 direction control
106 ICOC2_0 logical state
107 ICOC2_0 direction control
108 ICOC2_1 logical state
109 ICOC2_1 direction control
110 ICOC2_2 logical state
111 ICOC2_2 direction control
112 ICOC2_3 logical state
113 ICOC2_3 direction control
114 D0 logical state
115 D0 direction control
116 A0 logical state
117 A0 direction control
118 A1 logical state
119 A1 direction control
120 D1 logical state
121 D1 direction control
122 A2 logical state
123 A2 direction control
Bit
Logical State and Direction
Control Bits for Each Pin
124 D2 logical state
125 D2 direction control
126 D3 logical state
127 D3 direction control
128 D4 logical state
129 D4 direction control
130 D5 logical state
131 D5 direction control
132 D6 logical state
133 D6 direction control
134 D7 logical state
135 D7 direction control
136 D8 logical state
137 D8 direction control
138 D9 logical state
139 D9 direction control
140 D10 logical state
141 D10 direction control
142 D11 logical state
143 D11 direction control
144 D12 logical state
145 D12 direction control
146 D13 logical state
147 D13 direction control
148 D14 logical state
149 D14 direction control
150 A3 logical state
151 A3 direction control
152 A4 logical state
153 A4 direction control
JTAG Test Access Port and OnCE
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Technical Data
551