MMC2107 Datasheet, PDF (231/618 Pages) –

Freescale Semiconductor, Inc.
Clock Module
Memory Map and Registers
PLLMODE — Clock Mode Bit
The MODE bit is configured at reset and reflects the clock mode as
shown in Table 10-5.
1 = PLL clock mode
0 = External clock mode
Table 10-5. System Clock Modes
MODE:PLLSEL:PLLREF
Clock Mode
000
External clock mode
100
1:1 PLL mode
110
Normal PLL mode with external clock reference
111
Normal PLL mode with crystal oscillator
reference
PLLSEL — PLL Select Bit
The PLLSEL bit is configured at reset and reflects the PLL mode as
shown in Table 10-5.
1 = Normal PLL mode
0 = 1:1 PLL mode
PLLREF — PLL Reference Bit
The PLLREF bit is configured at reset and reflects the PLL reference
source in normal PLL mode as shown in Table 10-5.
1 = Crystal clock reference
0 = External clock reference
LOCKS — Sticky PLL Lock Bit
The LOCKS flag is a sticky indication of PLL lock status.
1 = No unintentional PLL loss of lock since last system reset or
MFD change
0 = PLL loss of lock since last system reset or MFD change or
currently not locked due to exit from STOP with FWKUP set
The lock detect function sets the LOCKS bit when the PLL achieves
lock after:
– A system reset, or
– A write to SYNCR that changes the MFD[2:0] bits
When the PLL loses lock, LOCKS is cleared. When the PLL relocks,
LOCKS remains cleared until one of the two listed events occurs.
MMC2107 – Rev. 2.0
MOTOROLA
Clock Module
For More Information On This Product,
Go to: www.freescale.com
Technical Data
231