MMC2107 Datasheet, PDF (303/618 Pages) –

Freescale Semiconductor, Inc.
Timer Modules (TIM1 and TIM2)
Memory Map and Registers
15.7.4 Timer Output Compare 3 Data Register
Address: TIM1 — 0x00ce_0003
TIM2 — 0x00cf_0003
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
OC3D3 OC3D2 OC3D1 OC3D0
Write:
Reset: 0
0
0
0
0
0
0
0
= Writes have no effect and the access terminates without a transfer error exception.
Figure 15-5. Timer Output Compare 3 Data Register (TIMOC3D)
Read: Anytime
Write: Anytime
OC3D[3:0] — Output Compare 3 Data Bits
When a successful channel 3 output compare occurs, these bits
transfer to the timer port data register if the corresponding OC3Mx bits
are set.
NOTE:
A successful channel 3 output compare overrides any channel 2:0
compares. For each OC3M bit that is set, the output compare action
reflects the corresponding OC3D bit.
MMC2107 – Rev. 2.0
MOTOROLA
Timer Modules (TIM1 and TIM2)
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Technical Data
303