MMC2107 Datasheet, PDF (605/618 Pages) –

Freescale Semiconductor, Inc.
Electrical Specifications
OnCE, JTAG, and Boundary Scan Timing
22.14 OnCE, JTAG, and Boundary Scan Timing
Table 22-14. OnCE, JTAG, and Boundary Scan Timing
(V_DD = 2.7 to 3.6 V, V_SS = 0 V, T_A = T_L to T_H)
No.
Characteristics
Symbol
Min
Max
Unit
1 TCLK frequency of operation
2 TCLK cycle period
3 TCLK clock pulse width
4 TCLK rise and fall times
5 Boundary scan input data setup time to TCLK rise
6 Boundary scan input data hold time after TCLK rise
f_JCYC
t_JCYC
t_JCW
t_JCRF
t_BSDST
t_BSDHT
dc
1/2 x f_sys MHz
2
—
t_cyc
25
—
ns
0
3
ns
5
—
ns
24
—
ns
7 TCLK low-to-boundary scan output data valid
t_BSDV
0
8 TCLK low-to-boundary scan output high Z
t_BSDZ
0
9 _{TMS, TDI, and DE input data setup time to TCLK rise}⁽¹⁾
t_TAPDST
7
40
ns
40
ns
—
ns
10 _{TMS, TDI, and DE input data hold time after TCLK rise}⁽¹⁾ t_TAPDHT
15
—
ns
11 TCLK low to TDO data valid
12 TCLK low to TDO high Z
13 TRST assert time
14 TRST setup time (negation) to TCLK high
15 _{DE input data setup time to CLKOUT rise}⁽¹⁾
t_TDODV
0
25
ns
t_TDODZ
0
9
ns
t_TRSTAT
100
—
ns
t_TRSTST
10
—
ns
t_DEDST
10
—
ns
16 _{DE input data hold time after CLKOUT rise}⁽¹⁾
t_DEDHT
2
—
ns
17 CLKOUT high to DE data valid
t_DEDV
0
20
ns
18 CLKOUT high to DE high Z
t_DEDZ
0
10
ns
1. Parameters 9 and 10 apply to the DE pin when used to enable OnCE. Parameters 15 and 16 apply to the DE pin when
used to request the processor to enter debug mode.
TCLK INPUT
MMC2107 – Rev. 2.0
MOTOROLA
2
3
3
V_IH
V_IL
4
4
Figure 22-9. Test Clock Input Timing
Electrical Specifications
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Go to: www.freescale.com
Technical Data
605