MMC2107 Datasheet, PDF (65/618 Pages) –

Freescale Semiconductor, Inc.
System Memory Map
Register Map
Address
0x00c4_0001
0x00c4_0002
0x00c4_0003
0x00c4_0004
↓
0x00c4_ffff
Register Name
Bit 7
Reset Status Register ^Read:
0
(RSR) Write:
See page 134. _Reset:
0
Bit 7
Read: 0
Reset Test Register
(RTR) Write:
See page 135. _Reset:
0
Bit 7
Reserved
Bit 7
Bit Number
6
5
4
3
2
1
Bit 0
0
SOFT WDR
POR
EXT
LOC
LOL
0
Reset dependent
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
Bit 0
Writes have no effect, reads return 0s, and the access terminates
without a transfer error exception.
6
5
4
3
2
1
Bit 0
Unimplemented
Access results in a bus monitor timeout generating an access termination transfer error.
Interrupt Controller (INTC)
0x00c5_0000
0x00c5_0001
Interrupt Control Register
(ICR)
See page 157.
Read:
Write:
Reset:
Read:
Write:
Reset:
0x00c5_0002
0x00c5_0003
Interrupt Status Register
(ISR)
See page 159.
Read:
Write:
Reset:
Read:
Write:
Reset:
Bit 15
AE
1
Bit 7
0
0
Bit 15
0
0
Bit 7
0
0
14
FVE
0
6
0
0
14
0
0
6
VEC6
0
13
12
11
10
0
0
ME
MFI
9
Bit 8
0
0
0
0
0
0
0
0
5
4
3
2
1
Bit 0
0
MASK4 MASK3 MASK2 MASK1 MASK0
0
0
0
0
0
0
13
12
11
10
9
Bit 8
0
0
0
0
INT
FINT
0
5
VEC5
0
4
VEC4
0
3
VEC3
0
2
VEC2
0
1
VEC1
0
Bit 0
VEC0
0
0
0
0
0
0
P = Current pin state
U = Unaffected
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 12 of 34)
MMC2107 – Rev. 2.0
MOTOROLA
System Memory Map
For More Information On This Product,
Go to: www.freescale.com
Technical Data
65