MMC2107 Datasheet, PDF (477/618 Pages) –

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Digital Control
SYSTEM CLOCK (f_sys)
HIGH-TIME
CYCLES (PSH) [5]
LOW-TIME
CYCLES (PSL) [3]
ZERO
DETECT
[5]
5-BIT
DOWN COUNTER
LOAD PSH
[3]
CLOCK
GENERATE
ONE’S COMPLEMENT
COMPARE
SET QCLK
QCLK
f_sys/2 to f_sys/40
INPUT SAMPLE TIME
FROM CCW [2]
ATD CONVERTER
STATE MACHINE
SAR CONTROL
SAR [10]
QUEUE1 AND QUEUE2 TIMER
MODE RATE SELECTION [8]
BINARY COUNTER
27 28 29 210 211 212 213 214 215 216 217
PERIODIC TIMER/INTERVAL TIMER
SELECT
PERIODIC/INTERVAL TRIGGER
EVENT FOR Q1 AND Q2 [2]
Figure 18-42. QADC Clock Subsystem Functions
To accommodate wide variations of the main MCU clock frequency
(IPbus system clock – f_sys), QCLK is generated by a programmable
prescaler which divides the MCU system clock. To allow the A/D
conversion time to be maximized across the spectrum of system clock
frequencies, the QADC prescaler permits the frequency of QCLK to be
software selectable. It also allows the duty cycle of the QCLK waveform
to be programmable.
The software establishes the basic high phase of the QCLK waveform
with the PSH (prescaler clock high time) field in QACR0 and selects the
basic low phase of QCLK with the PSL (prescaler clock low time) field.
The combination of the PSH and PSL parameters establishes the
frequency of the QCLK.
MMC2107 – Rev. 2.0
MOTOROLA
Queued Analog-to-Digital Converter (QADC)
For More Information On This Product,
Go to: www.freescale.com
Technical Data
477