MMC2107 Datasheet, PDF (569/618 Pages) –

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
Functional Description
SWO — Software Debug Occurrence Flag
SWO bit is set when the processor enters debug mode of operation
as a result of the execution of the BKPT instruction. This bit is cleared
on test logic reset or when debug mode is exited with the GO and EX
bits set.
TO — Trace Count Occurrence Flag
TO is set when the trace counter reaches zero with the trace mode
enabled and the CPU enters debug mode. This bit is cleared on test
logic reset or when debug mode is exited with the GO and EX bits set.
FRZO — FIFO Freeze Occurrence Flag
FRZO is set when a FIFO freeze occurs. This bit is cleared on test
logic reset or when debug mode is exited with the GO and EX bits set.
SQB — Sequential Breakpoint B Arm Occurrence Flag
SQB is set when sequential operation is enabled and a memory
breakpoint B event has occurred to enable trace counter operation.
This bit is cleared on test logic reset or when debug mode is exited
with the GO and EX bits set.
SQA — Sequential Breakpoint A Arm Occurrence Flag
SQA is set when sequential operation is enabled and a memory
breakpoint A event has occurred to enable memory breakpoint B
operation. This bit is cleared on test logic reset or when debug mode
is exited with the GO and EX bits set.
PM1 and PM0 — Processor Mode Field
These flags reflect the processor operating mode. They allow
coordination of the OnCE controller with the CPU for synchronization.
Table 21-7. Processor Mode Field Settings
PM1
and PM0
00
01
10
11
Meaning
Processor in normal mode
Processor in stop, doze, or wait mode
Processor in debug mode
Reserved
MMC2107 – Rev. 2.0
MOTOROLA
JTAG Test Access Port and OnCE
For More Information On This Product,
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Technical Data
569