MMC2107 Datasheet, PDF (459/618 Pages) –

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Digital Control
In situation 6 (Figure 18-28), the conversion initiated by the second
CCW in queue 2 is aborted just before the conversion is complete, so
that queue 1 execution can begin. Queue 2 is considered suspended.
After queue 1 is finished, queue 2 starts over with the first CCW, when
the RES (resume) control bit is set to 0. Situation S7 (Figure 18-29)
shows that when pause operation is not in use with queue 2, queue 2
suspension works the same way.
T1
T1
Q1: C1 C2
T2
PF1
Q2: C1 _C2
C3 C4
RESUME=0
CF1
C1 C2 C3 C4
Q1
IDLE
ACTIVE
PAUSE
AACCTTIIVVEE
CF2
IDLE
Q2
IDLE
ACTIVE
SUSPEND
ACTIVE
IDLE
QS
0000
1000
0100
0110
1010
0010
0000
Figure 18-28. CCW Priority Situation 6
T1
T1
Q1: C1 C2
T2
C3 C4
RESUME = 0
PF1
Q2:
C1 C2
CF1
C1 C2 C3 C4
Q1
IDLE
ACTIVE
PAUSE
AACCTTIIVVEE
CF2
IDLE
Q2
IDLE
ACTIVE
SUSPEND
ACTIVE
IDLE
QS
0000
1000
0100
0110
1010
0010
0000
Figure 18-29. CCW Priority Situation 7
MMC2107 – Rev. 2.0
MOTOROLA
Queued Analog-to-Digital Converter (QADC)
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Technical Data
459