MMC2107 Datasheet, PDF (305/618 Pages) –

Freescale Semiconductor, Inc.
Timer Modules (TIM1 and TIM2)
Memory Map and Registers
15.7.6 Timer System Control Register 1
Address: TIM1 — 0x00ce_0006
TIM2 — 0x00cf_0006
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
TIMEN
TFFCA
Write:
Reset: 0
0
0
0
0
0
0
0
= Writes have no effect and the access terminates without a transfer error exception.
Figure 15-8. Timer System Control Register (TIMSCR1)
Read: Anytime
Write: Anytime
TIMEN — Timer Enable Bit
TIMEN enables the timer. When the timer is disabled, only the
registers are accessible. Clearing TIMEN reduces power
consumption.
1 = Timer enabled
0 = Timer and timer counter disabled
TFFCA — Timer Fast Flag Clear All Bit
TFFCA enables fast clearing of the main timer interrupt flag registers
(TIMFLG1 and TIMFLG2) and the PA flag register (TIMPAFLG).
TFFCA eliminates the software overhead of a separate clear
sequence.
When TFFCA is set:
– An input capture read or a write to an output compare channel
clears the corresponding channel flag, CxF.
– Any access of the timer count registers (TIMCNTH/L) clears
the TOF flag.
– Any access of the PA counter registers (TIMPACNT) clears
both the PAOVF and PAIF flags in TIMPAFLG.
Writing logic 1s to the flags clears them only when TFFCA is clear.
1 = Fast flag clearing
0 = Normal flag clearing
MMC2107 – Rev. 2.0
MOTOROLA
Timer Modules (TIM1 and TIM2)
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Technical Data
305