MMC2107 Datasheet, PDF (323/618 Pages) –

Freescale Semiconductor, Inc.
Timer Modules (TIM1 and TIM2)
Functional Description
15.8.4 Pulse Accumulator
The pulse accumulator (PA) is a 16-bit counter that can operate in two
modes:
1. Event counter mode — Counts edges of selected polarity on the
pulse accumulator input pin, PAI
2. Gated time accumulation mode — Counts pulses from a
divide-by-64 clock
The PA mode bit, PAMOD, selects the mode of operation.
The minimum pulse width for the PAI input is greater than two module
clocks.
15.8.4.1 Event Counter Mode
Clearing the PAMOD bit configures the PA for event counter operation.
An active edge on the PAI pin increments the PA. The PA edge bit,
PEDGE, selects falling edges or rising edges to increment the PA.
An active edge on the PAI pin sets the PA input flag, PAIF. The PA input
interrupt enable bit, PAI, enables the PAIF flag to generate interrupt
requests.
NOTE:
The PAI input and timer channel 3 use the same pin. To use the PAI
input, disconnect it from the output logic by clearing the channel 3 output
mode and output level bits, OM3 and OL3. Also clear the channel 3
output compare 3 mask bit, OC3M3.
The PA counter registers, TIMPACNTH/L, reflect the number of active
input edges on the PAI pin since the last reset.
The PA overflow flag, PAOVF, is set when the PA rolls over from $FFFF
to $0000. The PA overflow interrupt enable bit, PAOVI, enables the
PAOVF flag to generate interrupt requests.
NOTE: The PA can operate in event counter mode even when the timer enable
bit, TIMEN, is clear.
MMC2107 – Rev. 2.0
MOTOROLA
Timer Modules (TIM1 and TIM2)
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Technical Data
323