MMC2107 Datasheet, PDF (164/618 Pages) –

Freescale Semiconductor, Inc.
Interrupt Controller Module
7.7.2.6 Normal Interrupt Pending Register
The read-only, 32-bit normal interrupt pending register (NIPR) reflects
any currently pending normal interrupts which are assigned to each
priority level. Writes to this register have no effect and are terminated
normally.
Address: 0x00c5_0014 through 0x00c5_0017
Bit 31
30
29
28
27
26
25
Bit 24
Read: NIP31 NIP30 NIP29 NIP28 NIP27 NIP26 NIP25 NIP24
Write:
Reset: 0
0
0
0
0
0
0
0
Bit 23
22
21
20
19
18
17
Bit 16
Read: NIP23 NIP22 NIP21 NIP20 NIP19 NIP18 NIP17 NIP16
Write:
Reset: 0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
Read: NIP15 NIP14 NIP13 NIP12 NIP11 NIP10 NIP9
NIP8
Write:
Reset: 0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
Read: NIP7
NIP6
NIP5
NIP4
NIP3
NIP2
NIP1
NIP0
Write:
Reset: 0
0
0
0
0
0
0
0
= Writes have no effect and the access terminates without a transfer error exception.
Figure 7-8. Normal Interrupt Pending Register (NIPR)
NIP[31:0] — Normal Interrupt Pending Field
A read-only NIPx bit is set when at least one normal interrupt request
is asserted at priority level x. Reset clears NIP[31:0].
1 = At least one normal interrupt request asserted at priority level x
0 = All normal interrupt requests at priority level x negated
Technical Data
164
Interrupt Controller Module
For More Information On This Product,
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA