MMC2107 Datasheet, PDF (480/618 Pages) –

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Example 1 in Figure 18-43 shows that when PSH = 11, the QCLK
remains high for 12 cycles of the system clock. It also shows that when
PSL = 7, the QCLK remains low for eight system clock cycles. In
Example 2, PSH = 7, and the QCLK remains high for eight cycles of the
system clock. It also shows that when PSL = 7, the QCLK remains low
for eight system clock cycles.
18.10.9 Periodic/Interval Timer
The on-chip periodic/interval timer can be used to generate trigger
events at a programmable interval, initiating execution of queue 1 and/or
queue 2. The periodic/interval timer stays reset under these conditions:
• Both queue 1 and queue 2 are programmed to any mode which
does not use the periodic/interval timer.
• IPbus system reset is asserted.
• Stop mode is selected.
• Debug mode is selected.
NOTE: Interval timer single-scan mode does not use the periodic/interval timer
until the single-scan enable bit is set.
These conditions will cause a pulsed reset of the periodic/interval timer
during use:
• A queue 1 operating mode change to a mode which uses the
periodic/interval timer, even if queue 2 is already using the timer
• A queue 2 operating mode change to a mode which uses the
periodic/interval timer, provided queue 1 is not in a mode which
uses the periodic/interval timer
• Roll over of the timer
During the low-power stop mode, the periodic/interval timer is held in
reset. Since low-power stop mode causes QACR1 and QACR2 to be
reset to 0, a valid periodic or interval timer mode must be written after
stop mode is exited to release the timer from reset.
When the IPbus internal FREEZE line is asserted and a periodic or
interval timer mode is selected, the timer counter is reset after the
conversion in progress completes. When the periodic or interval timer
Technical Data
480
Queued Analog-to-Digital Converter (QADC)
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MMC2107 – Rev. 2.0
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