MMC2107 Datasheet, PDF (572/618 Pages) –

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
21.14.7.1 Breakpoint Address Comparators
The breakpoint address comparators are not externally accessible. Each
compares the memory address stored in MAL with the contents of BABx,
as masked by BAMx, and signals the control logic when a match occurs.
21.14.7.2 Memory Breakpoint Counters
The 16-bit memory breakpoint counter registers (MBCA and MBCB) are
loaded with a value equal to the number of times, minus one, that a
memory access event should occur before a memory breakpoint is
declared. The memory access event is specified by the RCx4–RCx0 and
BCx4–BCx0 bits in the OCR and by the memory base and mask
registers. On each occurrence of the memory access event, the
breakpoint counter, if currently non-zero, is decremented. When the
counter has reached the value of zero and a new occurrence takes
place, the ISBKPTx signal is asserted and causes the CPU’s BRKRQ
input to be asserted. The MBCx can be read or written through the OnCE
serial interface.
Anytime the breakpoint registers are changed, or a different breakpoint
event is selected in the OCR, the breakpoint counter must be written
afterward. This assures that the OnCE breakpoint logic is reset and that
no previous events will affect the new breakpoint event selected.
21.14.8 OnCE Trace Logic
The OnCE trace logic allows the user to execute instructions in single or
multiple steps before the device returns to debug mode and awaits
OnCE commands from the debug serial port. The OnCE trace logic is
independent of the M•CORE trace facility, which is controlled through
the trace mode bits in the M•CORE processor status register. The OnCE
trace logic block diagram is shown in Figure 21-12.
Technical Data
572
JTAG Test Access Port and OnCE
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MMC2107 – Rev. 2.0
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