MMC2107 Datasheet, PDF (176/618 Pages) –

Freescale Semiconductor, Inc.
Static Random-Access Memory (SRAM)
8.4 Low-Power Modes
In wait, doze, and stop modes, clocks to the SRAM are disabled. No
recovery time is required when exiting any low-power mode.
8.5 Standby Power Supply Pin (V_STBY)
The standby power supply pin (V_STBY) provides standby voltage to the
RAM array if V_DD is lost. V_STBY is isolated from all other V_DD nodes.
8.6 Standby Operation
When the chip is powered down, the contents of the SRAM array are
maintained by the standby power supply, V_STBY. If the standby voltage
falls below the minimum required voltage, the SRAM contents may be
corrupted. The SRAM automatically switches to standby operation with
no loss of data when the voltage on V_DD is below the voltage on V_STBY.
In standby mode, the SRAM does not respond to any bus cycles.
Unexpected operation may occur if the central processor unit (CPU)
requests data from the SRAM in standby mode. If standby operation is
not needed, then the V_STBY pin should be connected to V_DD.
The current on V_STBY may exceed its specified maximum value at some
time during the transition time during which V_DD is at or below the
voltage switch threshold to a threshold above V_SS. If the standby power
supply cannot provide enough current to maintain V_STBY above the
required minimum value, then a capacitor must be provided from V_STBY
to V_SS. The value of the capacitor, C, can be calculated as:
where:
C
=
I×
--t-
V
I is the difference between the transition current requirement and the
maximum power supply current,
t is the duration of the V_DD transition near the voltage switch
threshold, and
V is the difference between the minimum available supply voltage and
the required minimum V_STBY voltage.
Technical Data
176
Static Random-Access Memory (SRAM)
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MMC2107 – Rev. 2.0
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