MMC2107 Datasheet, PDF (540/618 Pages) –

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
21.4 Top-Level TAP Controller
The top-level TAP controller is responsible for interpreting the sequence
of logical values on the TMS signal. It is a synchronous state machine
that controls the operation of the JTAG logic. The machine’s states are
shown in Figure 21-2. The value shown adjacent to each arc represents
the value of the TMS signal sampled on the rising edge of the TCLK
signal.
The top-level TAP controller can be asynchronously reset to the test-
logic-reset state by asserting TRST, test reset. As Figure 21-2 shows,
holding TMS high (to logic 1) while clocking TCLK through at least five
rising edges will also cause the state machine to enter its test-logic-reset
state.
TEST-LOGIC-
RESET
1
0
1
RUN-TEST/IDLE
1
SELECT-DR_SCAN
0
0
1
CAPTURE-DR
0
SHIFT-DR
1
0
EXIT1-DR
1
0
PAUSE-DR
1
0
0
EXIT2-DR
1
UPDATE-DR
1
0
1
SELECT-IR_SCAN
0
1
CAPTURE-IR
0
SHIFT-IR
10
EXIT1-IR
1
0
PAUSE-IR
10
0
EXIT2-IR
1
UPDATE-IR
1
0
Technical Data
540
Figure 21-2. Top-Level TAP Controller State Machine
JTAG Test Access Port and OnCE
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Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA