MMC2107 Datasheet, PDF (200/618 Pages) –

Freescale Semiconductor, Inc.
Non-Volatile Memory FLASH (CMFR)
CLKPM[6:0] — Clock Period Multiplier Field
The third term of the timing control is the linear clock multiplier, M. The
clock period multiplier, CLKPM[6:0], defines a linear multiplier for the
program or erase pulse. M is defined by:
M = 1 + (CLKPM[6:0])
This allows the program/erase pulse to be from 1 to 128 times the
pulse set by the system clock period, SCLKR[2:0] and CLKPE[1:0].
The default reset state of CLKPM[6:0] is binary 000 0000, which gives
a multiplier of 1.
NOTE:
The CLKPM[6:0] bits are not write protected by the SES bit. Unless the
PAWS[2] bit is set, writes to CLKPM[6:0] in software should not be
changed if SES = 1.
Table 9-6 shows an example of calculating the values of SCLKR[2:0],
CLKPE[1:0] and CLKPM[6:0] for a 1-ms program pulse, ERASE = 0,
in a system with a 33.0-MHz system clock having a period of 30.3 ns.
Table 9-6. Determining SCLKR[2:0], CLKPE[1:0],
and CLKPM[6:0]
No.
Example Calculation
1
Determine SCLKR[2:0] — Table 9-4 shows that a SCLKR[2:0] value of 100
and an R value of 3 gives a system clock frequency from 24 MHz to 36 MHz.
Determine CLKPE[1:0] — 9.7.1 Control Registers shows that when
2
ERASE = 0, a 1-ms program pulse can be generated by an N value of 7
(CLKPE[1:0] = 10) or 8 (CLKPE[1:0] = 11). An N value of 8 is used in this
example.
Determine CLKPM[6:0] — Using the selected values of N and R in the pulse
3
width equation, pulse width = system clock period × R × 2^N × M and solving
for M yields 42.97. Rounding M to 43 and using the M equation,
M = 1 + (CLKPM[6:0]) and solving for CLKPM[6:0] yields 42.
Check the results — pulse width = 30.3 ns × 3 × 2⁸ × 43 = 1.00 ms where
4 _{SCLKR[2:0] = 100, CLKPE[1:0] = 11, CLKPM[6:0] = 0101010, ERASE = 0,}
system clock frequency = 33.0 MHz
Technical Data
200
Non-Volatile Memory FLASH (CMFR)
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MMC2107 – Rev. 2.0
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