MMC2107 Datasheet, PDF (370/618 Pages) –

Freescale Semiconductor, Inc.
Serial Communications Interface Modules (SCI1 and SCI2)
16.17.3 Receive Data Register Full
The RDRF flag is set when the data in the receive shift register transfers
to SCIDRH and SCIDRL. It signals that the received data is available to
be read. If the RIE bit is set in SCICR2, RDRF generates an interrupt
request. Clear RDRF by reading SCISR1 and then reading SCIDRL.
16.17.4 Idle Receiver Input
The IDLE flag is set when 10 (if M = 0) or 11 (if M = 1) consecutive
logic 1s appear on the receiver input. This signals an idle condition on
the receiver input. If the ILIE bit in SCICR2 is set, IDLE generates an
interrupt request. Once IDLE is cleared, a valid frame must again set the
RDRF flag before an idle condition can set the IDLE flag. Clear IDLE by
reading SCISR1 with IDLE set and then reading SCIDRL.
16.17.5 Overrun
The OR flag is set if data is not read from SCIDRL before the receive
shift register receives the stop bit of the next frame. This signals a
receiver overrun condition. If the RIE bit in SCICR2 is set, OR generates
an interrupt request. The data in the shift register is lost, but the data
already in SCIDRH and SCIDRL is not affected. Clear OR by reading
SCISR1 and then reading SCIDRL.
Technical Data
370
Serial Communications Interface Modules (SCI1 and SCI2)
For More Information On This Product,
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA