MMC2107 Datasheet, PDF (312/618 Pages) –

Freescale Semiconductor, Inc.
Timer Modules (TIM1 and TIM2)
15.7.12 Timer Flag Register 1
Address: TIM1 — 0x00ce_000e
TIM2 — 0x00cf_000e
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
C3F
C2F
C1F
C0F
Write:
Reset: 0
0
0
0
0
0
0
0
= Writes have no effect and the access terminates without a transfer error exception.
Figure 15-15. Timer Flag Register 1 (TIMFLG1)
Read: Anytime
Write: Anytime; writing 1 clears flag; writing 0 has no effect
C[3:0]F — Channel Flags
A channel flag is set when an input capture or output compare event
occurs. Clear a channel flag by writing a 1 to it.
NOTE:
When the fast flag clear all bit, TFFCA, is set, an input capture read or
an output compare write clears the corresponding channel flag. TFFCA
is in timer system control register 1 (TIMSCR1).
When a channel flag is set, it does not inhibit subsequent output
compares or input captures.
Technical Data
312
Timer Modules (TIM1 and TIM2)
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MMC2107 – Rev. 2.0
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