MMC2107 Datasheet, PDF (390/618 Pages) –

Freescale Semiconductor, Inc.
Serial Peripheral Interface Module (SPI)
When CPHA = 1, the slave SS line can remain low between bytes. This
format is good for systems with a single master and a single slave driving
the MISO data line.
Writing to SPIDR while a transmission is in progress sets the WCOL flag
to indicate a write collision and inhibits the write. WCOL does not
generate an interrupt request; the SPIF interrupt request comes at the
end of the transfer that was in progress at the time of the error.
17.8.3.2 Transfer Format When CPHA = 0
In some peripherals, the slave MSB is available at its MISO pin as soon
as the slave is selected. When the CPHA bit is clear, the master SPI
delays its first SCK edge for half a SCK cycle after the transmission
starts. The first edge and all following odd-numbered edges latch the
slave data. Even-numbered SCK edges shift slave data into the master
shift register and shift master data out on the master MOSI pin.
After the 16th and final SCK edge:
• Data that was in the master SPIDR is in the slave SPIDR. Data
that was in the slave SPIDR is in the master SPIDR.
• The SCK clock stops and the SPIF flag in SPISR is set, indicating
that the transmission is complete. If the SPIE bit in SPCR1 is set,
SPIF generates an interrupt request.
Figure 17-12 shows the timing of a transmission with the CPHA bit clear.
The SS pin of the master must be either high or configured as a
general-purpose output not affecting the SPI.
Technical Data
390
Serial Peripheral Interface Module (SPI)
For More Information On This Product,
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA