MMC2107 Datasheet, PDF (525/618 Pages) –

Freescale Semiconductor, Inc.
Chip Select Module
Memory Map and Registers
20.6.2 Registers
The chip programming model consists of four chip select control
registers (CSCR0–CSCR3), one for each chip select (CS[3:0]).
CSCR0–CSCR3 are read/write always and define the conditions for
asserting the chip select signals.
All the chip select control registers are the same except for the reset
states of the CSEN and PS bits in CSCR0 and the CSEN bit in CSCR1.
This allows CS0 to be enabled at reset with either a 16-bit or 32-bit port
size for selecting an external boot device and allows CS1 to be used to
emulate internal memory.
Address: 0x00c2_0000 and 0x00c2_0001
Bit 15
14
13
12
11
10
9
Bit 8
Read:
SO
RO
PS
WWS
WE
WS2
WS1
WS0
Write:
Reset: 0
0
See note
1
1
1
1
1
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
0
0
TAEN CSEN
Write:
Reset: 0
0
0
0
0
0
1
See note
= Writes have no effect and the access terminates without a transfer error exception.
Note: Reset state determined during reset configuration.
Figure 20-2. Chip Select Control Register 0 (CSCR0)
MMC2107 – Rev. 2.0
MOTOROLA
Chip Select Module
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Technical Data
525