MMC2107 Datasheet, PDF (72/618 Pages) –

Freescale Semiconductor, Inc.
System Memory Map
Address
0x00c7_0006
0x00c7_0007
0x00c7_0008
↓
0x00c7_ffff
Register Name
Bit Number
Bit 15
14
13
12
11
10
9
Bit 8
Watchdog Service Read:
Register (WSR)
See page 279.
Write:
WS15
WS14
WS13
WS12
WS11
WS10
WS9
WS8
Reset: 0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
WS7
WS6
WS5
WS4
WS3
WS2
WS1
WS0
Write:
Reset: 0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
Unimplemented
Access results in a bus monitor timeout generating an access termination transfer error.
Programmable Interrupt Timer 1 (PIT1) and Programming Interrupt Timer 2 (PIT2)
Note: Addresses for PIT1 are at 0x00c8_#### and addresses for PIT2 are at 0x00c9_####.
Bit 15
14
13
12
0x00c8_0000 PIT Control and Status Read: 0
0
0
0
0x00c8_0001
0x00c9_0000
Register (PCSR)
See page 285. ^Write:
0x00c9_0001
Reset: 0
0
0
0
Bit 7
6
5
4
Read: 0
Write:
PDOZE PDBG OVW
Reset: 0
0
0
0
Bit 15
14
13
12
0x00c8_0002
0x00c8_0003
0x00c9_0002
0x00c9_0003
PIT Modulus Register
(PMR)
See page 288.
Read:
Write:
Reset:
PM15
1
PM14
1
PM13
1
PM12
1
Bit 7
6
5
4
Read:
PM7
PM6
PM5
PM4
Write:
Reset: 1
1
1
1
11
PRE3
0
3
PIE
0
11
PM11
1
3
PM3
1
10
PRE2
0
2
PIF
0
10
PM10
1
2
PM2
1
9
PRE1
0
1
RLD
0
9
PM9
1
1
PM1
1
Bit 8
PRE0
0
Bit 0
EN
0
Bit 8
PM8
1
Bit 0
PM0
1
P = Current pin state
U = Unaffected
= Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 19 of 34)
Technical Data
72
System Memory Map
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MMC2107 – Rev. 2.0
MOTOROLA