MMC2107 Datasheet, PDF (546/618 Pages) –

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
21.7 Bypass Register
The MMC2107 includes an IEEE 1149.1 standard-compliant bypass
register, which creates a single bit shift register path from TDI to the
bypass register to TDO when the BYPASS instruction is selected.
21.8 Boundary SCAN Register
MMC2107 includes an IEEE 1149.1 standard-compliant boundary-scan
register. The boundary-scan register is connected between TDI and
TDO when the EXTEST or SAMPLE/PRELOAD instructions are
selected. This register captures signal pin data on the input pins, forces
fixed values on the output signal pins, and selects the direction and drive
characteristics (a logic value or high impedance) of the bidirectional and
three-state signal pins.
21.9 Restrictions
The test logic is implemented using static logic design, and TCLK can be
stopped in either a high or low state without loss of data. The system
logic, however, operates on a different system clock which is not
synchronized to TCLK internally. Any mixed operation requiring the use
of the IEEE 1149.1 standard test logic, in conjunction with system
functional logic that uses both clocks, must have coordination and
synchronization of these clocks done externally.
The control afforded by the output enable signals using the boundary
scan register and the EXTEST instruction requires a compatible
circuit-board test environment to avoid device-destructive
configurations. The user must avoid situations in which MMC2107
output drivers are enabled into actively driven networks.
Technical Data
546
JTAG Test Access Port and OnCE
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MMC2107 – Rev. 2.0
MOTOROLA