MMC2107 Datasheet, PDF (448/618 Pages) –

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
NOTE:
If the amplifier bypass mode is enabled for a conversion by setting the
amplifier bypass (BYP) field in the CCW, the timing changes to that
shown in Figure 18-21. See 18.8.7 Conversion Command Word
Table for more information on the BYP field. The initial sample time is
eliminated, reducing the potential conversion time by two QCLKs. When
using the bypass mode, the external circuit should be of low source
impedance (typically less than 10 kΩ). Also, the loading effects to the
external circuitry by the QADC need to be considered, since the benefits
of the sample amplifier are not present.
Because of internal RC time constants, it is not recommended to use a
sample time of two QCLKs in bypass mode for high-frequency operation.
SAMPLE
TIME:
N CYCLES
(2,4,8,16)
RESOLUTION
TIME:
10 CYCLES
QCLK
SAMPLE TIME
SUCCESSIVE-APPROXIMATION RESOLUTION SEQUENCE
Figure 18-21. Bypass Mode Conversion Timing
18.9.3.3 Channel Decode and Multiplexer
The internal multiplexer selects one of the eight analog input pins for
conversion. The selected input is connected to the Sample Buffer
Amplifier or to the sample capacitor. The multiplexer also includes
positive and negative stress protection circuitry, which prevents
deselected channels from affecting the selected channel when current is
injected into the deselected channels.
18.9.3.4 Sample Buffer
The sample buffer is used to raise the effective input impedance of the
A/D converter, so that external components (higher bandwidth or higher
impedance) are less critical to accuracy. The input voltage is buffered
onto the sample capacitor to reduce crosstalk between channels.
Technical Data
448
Queued Analog-to-Digital Converter (QADC)
For More Information On This Product,
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA