MMC2107 Datasheet, PDF (299/618 Pages) –

Freescale Semiconductor, Inc.
Timer Modules (TIM1 and TIM2)
Memory Map and Registers
Table 15-2. Timer Modules Memory Map
Address
TIM1
TIM2
0x00ce_0000 0x00cf_0000
0x00ce_0001 0x00cf_0001
0x00ce_0002 0x00cf_0002
0x00ce_0003 0x00cf_0003
0x00ce_0004 0x00cf_0004
0x00ce_0005 0x00cf_0005
0x00ce_0006 0x00cf_0006
0x00ce_0007 0x00cf_0007
0x00ce_0008 0x00cf_0008
0x00ce_0009 0x00cf_0009
0x00ce_000a 0x00cf_000a
0x00ce_000b 0x00cf_000b
0x00ce_000c 0x00cf_000c
0x00ce_000d 0x00cf_000d
0x00ce_000e 0x00cf_000e
0x00ce_000f 0x00cf_000f
0x00ce_0010 0x00cf_0010
0x00ce_0011 0x00cf_0011
0x00ce_0012 0x00cf_0012
0x00ce_0013 0x00cf_0013
0x00ce_0014 0x00cf_0014
0x00ce_0015 0x00cf_0015
0x00ce_0016 0x00cf_0016
0x00ce_0017 0x00cf_0017
0x00ce_0018 0x00cf_0018
0x00ce_0019 0x00cf_0019
0x00ce_001a 0x00cf_001a
0x00ce_001b 0x00cf_001b
0x00ce_001c 0x00cf_001c
0x00ce_001d 0x00cf_001d
0x00ce_001e 0x00cf_001e
0x00ce_001f 0x00cf_001f
Bits 7–0
Timer IC/OC select register (TIMIOS)
Timer compare force register (TIMCFORC)
Timer output compare 3 mask register (TIMOC3M)
Timer output compare 3 data register (TIMOC3D)
Timer counter register high (TIMCNTH)
Timer counter register low (TIMCNTL)
Timer system control register 1 (TIMSCR1)
Reserved⁽²⁾
Timer toggle-on-overflow register (TMTOV)
Timer control register 1 (TIMCTL1)
Reserved⁽²⁾
Timer control register 2 (TIMCTL2)
Timer interrupt enable register (TIMIE)
Timer system control register 2 (TIMSCR2)
Timer flag register 1 (TIMFLG1)
Timer flag register 2 (TIMFLG2)
Timer channel 0 register high (TIMC0H)
Timer channel 0 register low (TIMC0L)
Timer channel 1 register high (TIMC1H)
Timer channel 1 register low (TIMC1L)
Timer channel 2 register high (TIMC2H)
Timer channel 2 register low (TIMC2L)
Timer channel 3 register high (TIMC3H)
Timer channel 3 register low (TIMC3L)
Pulse accumulator control register (TIMPACTL)
Pulse accumulator flag register (TIMPAFLG)
Pulse accumulator counter register high (TIMPACNTH)
Pulse accumulator counter register low (TIMPACNTL)
Reserved⁽²⁾
Timer port data register (TIMPORT)
Timer port data direction register (TIMDDR)
Timer test register (TIMTST)
1. S = CPU supervisor mode access only.
2. Writes have no effect, reads return 0s, and the access terminates without a transfer error exception.
Access⁽¹⁾
S
S
S
S
S
S
S
—
S
S
—
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
—
S
S
S
MMC2107 – Rev. 2.0
MOTOROLA
Timer Modules (TIM1 and TIM2)
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Technical Data
299