MMC2107 Datasheet, PDF (558/618 Pages) –

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
For accesses to the CPU internal state, the OnCE controller requests the
CPU to enter debug mode via the CPU DBGRQ input. Once the CPU
enters debug mode, as indicated by the OnCE status register, the
processor state may be accessed through the CPU scan register.
The OnCE controller is implemented as a 16-state finite state machine,
with a one-to-one correspondence to the states defined for the JTAG
TAP controller.
CPU registers and the contents of memory locations are accessed by
scanning instructions and data into and out of the CPU scan chain.
Required data is accessed by executing the scanned instructions.
Memory locations may be read by scanning in a load instruction to the
CPU that references the desired memory location, executing the load
instruction, and then scanning out the result of the load. Other resources
are accessed in a similar manner.
Resources contained in the OnCE module that do not require the CPU
to be halted for access may be controlled while the CPU is executing and
do not interfere with normal processor execution. Accesses to certain
resources, such as the PC FIFO and the count registers, while not part
of the CPU, may require the CPU to be stopped to allow access to avoid
synchronization hazards. If it is known that the CPU clock is enabled and
running no slower than the TCLK input, there is sufficient
synchronization performed to allow reads but not writes of these specific
resources. Debug firmware may ensure that it is safe to access these
resources by reading the OSR to determine the state of the CPU prior to
access. All other cases require the CPU to be in the debug state for
deterministic operation.
21.14.2 OnCE Controller and Serial Interface
Figure 21-7 is a block diagram of the OnCE controller and serial
interface.
The OnCE command register acts as the instruction register (IR) for the
TAP controller. All other OnCE resources are treated as data registers
(DR) by the TAP controller. The command register is loaded by serially
shifting in commands during the TAP controller shift-IR state, and is
loaded during the update-IR state. The command register selects a
Technical Data
558
JTAG Test Access Port and OnCE
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MMC2107 – Rev. 2.0
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