MMC2107 Datasheet, PDF (250/618 Pages) –

Ports Module
Freescale Semiconductor, Inc.
11.4.1 Memory Map
Table 11-1. I/O Port Module Memory Map
Address
Bits 31–24
Bits 23–16
Bits 15–8
Bits 7–0
Access⁽¹⁾
0x00c0_0000
PORTA
PORTB
PORTC
PORTD
S/U
0x00c0_0004
PORTE
PORTF
PORTG
PORTH
S/U
0x00c0_0008
PORTI
Reserved⁽²⁾
S/U
0x00c0_000c
DDRA
DDRB
DDRC
DDRD
S/U
0x00c0_0010
DDRE
DDRF
DDRG
DDRH
S/U
0x00c0_0014
DDRI
Reserved⁽²⁾
S/U
0x00c0_0018 PORTAP/SETA PORTBP/SETB PORTCP/SETC PORTDP/SETD
S/U
0x00c0_001c PORTEP/SETE PORTFP/SETF PORTGP/SETG PORTHP/SETH
S/U
0x00c0_0020 PORTIP/SETI
Reserved⁽²⁾
S/U
0x00c0_0024
CLRA
CLRB
CLRC
CLRD
S/U
0x00c0_0028
CLRE
CLRF
CLRG
CLRH
S/U
0x00c0_002c
CLRI
Reserved⁽²⁾
S/U
0x00c0_0030
PCDPAR
PEPAR
Reserved⁽²⁾
S/U
0x00c0_0034–
0x00c0_003c
Reserved⁽²⁾
S/U
1. S/U = CPU supervisor or user mode access. User mode accesses to supervisor only addresses have no effect and result
in a cycle termination transfer error.
2. Writes have no effect, reads return 0s, and the access terminates without a transfer error exception.
Technical Data
250
Ports Module
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MMC2107 – Rev. 2.0
MOTOROLA