MMC2107 Datasheet, PDF (144/618 Pages) –

Freescale Semiconductor, Inc.
M•CORE M210 Central Processor Unit (CPU)
6.3 Features
The streamlined execution engine uses many of the same performance
enhancements and implementation techniques incorporated in desktop
RISC processors. A strictly defined load/store architecture minimizes
control complexity. Use of a fixed, 16-bit instruction encoding
significantly lowers the memory bandwidth needed to sustain a high rate
of instruction execution, and careful selection of the instruction set
allows the code density and overall memory efficiency of the M•CORE
architecture to surpass those of complex instruction set computer
(CISC) architectures.
These factors reduce system energy consumption significantly, and the
fully static M•CORE design uses other techniques to reduce it even
more. The core uses dynamic clock management to automatically
power-down internal functions that are not in use on a clock-by-clock
basis. It also incorporates three power-conservation operating modes,
which are invoked via dedicated instructions.
The main features of the M•CORE are:
• 32-bit load/store RISC architecture
• Fixed 16-bit instruction length
• 16 entry, 32-bit general-purpose register file
• Efficient 4-stage execution pipeline, hidden from application
software
• Single-cycle execution for most instructions, 2-cycle branches and
memory accesses
• Support for byte/half-word/word memory access
• Fast interrupt support, with 16 entry user-controlled alternate
register file
• Vectored and autovectored interrupt support
• On-chip emulation support
• Full static design for minimal power consumption
Technical Data
144
M•CORE M210 Central Processor Unit (CPU)
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MMC2107 – Rev. 2.0
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