MMC2107 Datasheet, PDF (166/618 Pages) –

Freescale Semiconductor, Inc.
Interrupt Controller Module
7.7.2.8 Fast Interrupt Pending Register
The read-only, 32-bit fast interrupt pending register (FIPR) reflects any
currently pending fast interrupts which are assigned to each priority
level. Writes to this register have no effect and are terminated normally.
Address: 0x00c5_001c through 0x00c5_001f
Bit 31
30
29
28
27
26
25
Bit 24
Read: FIP31 FIP30 FIP29 FIP28 FIP27 FIP26 FIP25 FIP24
Write:
Reset: 0
0
0
0
0
0
0
0
Bit 23
22
21
20
19
18
17
Bit 16
Read: FIP23 FIP22 FIP21 FIP20 FIP19 FIP18 FIP17 FIP16
Write:
Reset: 0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
Bit 8
Read: FIP15 FIP14 FIP13 FIP12 FIP11 FIP10 FIP9
FIP8
Write:
Reset: 0
0
0
0
0
0
0
0
Bit 7
6
5
4
3
2
1
Bit 0
Read: FIP7
FIP6
FIP5
FIP4
FIP3
FIP2
FIP1
FIP0
Write:
Reset: 0
0
0
0
0
0
0
0
= Writes have no effect and the access terminates without a transfer error exception.
Figure 7-10. Fast Interrupt Pending Register (FIPR)
FIP[31:0] — Fast Interrupt Pending Field
A read-only FIP[x] bit is set when at least one interrupt request at
priority level x is pending and enabled as a fast interrupt. Reset clears
FIP[31:0].
1 = At least one fast interrupt request asserted at priority level x
0 = Any fast interrupt requests at priority level x negated
Technical Data
166
Interrupt Controller Module
For More Information On This Product,
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA