MMC2107 Datasheet, PDF (313/618 Pages) –

Freescale Semiconductor, Inc.
Timer Modules (TIM1 and TIM2)
Memory Map and Registers
15.7.13 Timer Flag Register 2
Address: TIM1 — 0x00ce_000f
TIM2 — 0x00cf_000f
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
0
TOF
Write:
Reset: 0
0
0
0
0
0
0
0
= Writes have no effect and the access terminates without a transfer error exception.
Figure 15-16. Timer Flag Register 2 (TIMFLG2)
Read: Anytime
Write: Anytime; writing 1 clears flag; writing 0 has no effect
TOF — Timer Overflow Flag
TOF is set when the timer counter rolls over from $FFFF to $0000. If
the TOI bit in TIMSCR2 is also set, TOF generates an interrupt
request. Clear TOF by writing a 1 to it.
1 = Timer overflow
0 = No timer overflow
NOTE:
When the timer channel 3 registers contain $FFFF and TCRE is set,
TOF never gets set even though the timer counter registers go from
$FFFF to $0000.
When the fast flag clear all bit, TFFCA, is set, any access to the timer
counter registers clears timer flag register 2. The TFFCA bit is in timer
system control register 1 (TIMSCR1).
When TOF is set, it does not inhibit subsequent overflow events.
MMC2107 – Rev. 2.0
MOTOROLA
Timer Modules (TIM1 and TIM2)
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Technical Data
313