MMC2107 Datasheet, PDF (593/618 Pages) –

Freescale Semiconductor, Inc.
Electrical Specifications
QADC Electrical Characteristics
Table 22-8. QADC Conversion Specifications
(V_DDH and V_DDA = 5.0 Vdc ± 0.5 V, V_DD = 2.7 to 3.6 V, V_SS = V_SSA = 0 Vdc,
V_RH – V_RL = 5 V ± 0.5 V, T_A = T_L to T_H)
No.
Parameter
1 _{QADC clock (QCLK) frequency}⁽¹⁾
2 Conversion cycles
Symbol
Min
f_QCLK
0.5
CC
14
Max
2.1
28
Unit
MHz
QCLK
cycles
Conversion time, f_QCLK = 2.0 MHz
3
Minimum = CCW/IST =%00
Maximum = CCW/IST =%11
t_CONV
7.0
4 Stop mode recovery time
t_SR
—
5 _Resolution⁽²⁾
—
5
Absolute (total unadjusted) error^{(3), (4), (5)}
6
f_QCLK = 2.0 MHz⁽²⁾, two clock input sample time
AE
–2
7 _{Disruptive input injection current}^{(6), (7), (8)}
I_INJ(9)
–1
14.0
10
—
2
1
µs
µs
mV
Counts
mA
Current coupling ratio⁽¹⁰⁾
8
PQA
PQB
K
—
8x10 ^–5
m
—
8x10 ^–5
Incremental error due to injection current
9
All channels have same 10 kΩ < R_S <100 kΩ
Channel under test has R_S = 10 kΩ,
E_INJ
—
—
I_INJ = I_INJMAX, I_INJMIN
—
10 _{Source impedance at input}⁽¹¹⁾
R_S
—
11 _{Incremental capacitance during sampling}⁽¹²⁾
C_SAMP
—
+1.0
+1.0
+1.0
100
5
Counts
Counts
Counts
kΩ
pF
1. Conversion characteristics vary with f_QCLK rate. Reduced conversion accuracy occurs at max f_QCLK rate. Using the QADC
pins as GPIO functions during conversions may result in degraded results.
2. At V_RH – V_RL = 5.12 V, one count = 5 mV
3. Accuracy tested and guaranteed at V_RH – V_RL = 5.0 V ± 0.5 V
4. Absolute error includes 1/2 count (~2.5 mV) of inherent quantization error and circuit (differential, integral, and offset) error.
Specification assumes that adequate low-pass filtering is present on analog input pins — capacitive filter with 0.01 µF to
0.1 µF capacitor between analog input and analog ground, typical source isolation impedance of 10 kΩ.
5. Input signals with large slew rates or high frequency noise components cannot be converted accurately. These signals may
affect the conversion accuracy of other channels
6. Below disruptive current conditions, the channel being stressed has conversion values of $3FF for analog inputs greater
than V_RH and $000 for values less than V_RL. This assumes that V_RH < V_DDA and V_RL > V_SSA due to the presence of the
sample amplifier. Other channels are not affected by non-disruptive conditions.
7. Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit
do not affect device reliability or cause permanent damage.
8. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values using V_POSCLAMP = V_DDA + 0.5 V and V_NEGCLAMP = – 0.3 V, then use the larger of the calculated values.
9. Condition applies to two adjacent pins.
10. Current coupling ratio, K, is defined as the ratio of the output current, I_Out, measured on the pin under test to the injection
current, I_INJ, when both adjacent pins are overstressed with the specified injection current. K = I_Out/ I_INJ The input voltage
error on the channel under test is calculated as V_ERR = I_INJ x K x R_S.
— Continued —
MMC2107 – Rev. 2.0
MOTOROLA
Electrical Specifications
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Technical Data
593