MMC2107 Datasheet, PDF (408/618 Pages) –

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Since port QB pins are input only, a data direction register is not
necessary. The digital input signal states are read by the software in the
lower half of the port data register.
18.6.3 External Trigger Input Pins
The QADC uses two external trigger pins (ETRIG[2:1]). Each of the two
input external trigger pins is associated with one of the scan queues,
queue 1 or queue 2. The assignment of ETRIG[2:1] to a queue is made
in QACR0 by the TRG bit. When TRG = 0, ETRIG1 triggers queue 1 and
ETRIG2 triggers queue 2. When TRG = 1, ETRIG1 triggers queue 2 and
ETRIG2 triggers queue 1.
18.6.4 Multiplexed Address Output Pins
In the non-multiplexed mode, the eight channel pins are connected to an
internal multiplexer which routes the analog signals into the internal A/D
converter.
In the externally multiplexed mode, the QADC allows automatic channel
selection through up to four external 4-to-1 selector chips. The QADC
provides a 2-bit multiplexed address output to the external multiplex
chips to allow selection of one of four inputs. The multiplexed address
output signals (MA[1:0]) can be used as multiplexed address output bits
or as general-purpose I/O.
MA[1:0] are used as the address inputs for one to two dual 4-channel
multiplexer chips. Since the MA[1:0] pins are digital outputs in the
multiplexed mode, the software programmed input/output direction for
the multiplexed address pins in the data direction register is superseded.
Technical Data
408
Queued Analog-to-Digital Converter (QADC)
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MMC2107 – Rev. 2.0
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