MMC2107 Datasheet, PDF (429/618 Pages) –

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Register Descriptions
In external gated single-scan and continuous-scan mode, the
definition of PF1 has been redefined. When the gate closes before the
end-of-queue 1 is reached, PF1 becomes set to indicate that an
incomplete scan has occurred. In single-scan mode, setting PF1 can
be used to cause an interrupt and software can then determine if
queue 1 should be enabled again. In either external gated mode,
setting PF1 indicates that the results for queue 1 have not been
collected during one scan (coherently).
NOTE:
If a pause in a CCW is encountered in external gated mode for either
single-scan and continuous-scan mode, the pause flag will not set, and
execution continues without pausing. This has allowed for the added
definition of PF1 in the external gated modes.
PF1 is maintained by the QADC regardless of whether the
corresponding interrupts are enabled. The software may poll PF1 to
find out when the QADC has reached a pause in scanning a
queue.The software acknowledges that it has detected a pause flag
being set by writing a 0 to PF1 after the bit was last read as a 1.
1 = Queue 1 has reached a pause or gate closed before
end-of-queue in gated mode.
0 = Queue 1 has not reached a pause or gate has not closed before
end-of-queue in gated mode.
See Table 18-7 for a summary of pause response in all scan modes.
Table 18-7. Pause Response
Scan Mode
External trigger single-scan
External trigger continuous-scan
Interval timer trigger single-scan
Interval timer continuous-scan
Software-initiated single-scan
Software-initiated continuous-scan
External gated single-scan
External gated continuous-scan
Queue Operation
Pauses
Pauses
Pauses
Pauses
Continues
Continues
Continues
Continues
PF Asserts?
Yes
Yes
Yes
Yes
Yes
Yes
No
No
MMC2107 – Rev. 2.0
MOTOROLA
Queued Analog-to-Digital Converter (QADC)
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Technical Data
429