MMC2107 Datasheet, PDF (167/618 Pages) –

Freescale Semiconductor, Inc.
Interrupt Controller Module
Functional Description
7.7.2.9 Priority Level Select Registers
There are 40 read/write, 8-bit priority level select registers
PLSR0–PLSR39, one for every interrupt source. The PLSRx register
assigns a priority level to interrupt source x.
Address: 0x00c5_0040 through 0x00c5_0067
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
PLS4 PLS3 PLS2 PLS1 PLS0
Write:
Reset: 0
0
0
0
0
0
0
0
= Writes have no effect and the access terminates without a transfer error exception.
Figure 7-11. Priority Level Select Registers (PLSR0–PLSR39)
PLS[4:0] — Priority Level Select Field
The PLS[4:0] field assigns a priority level from 0 to 31 to the
corresponding interrupt source. Reset clears PLS[4:0].
Table 7-3. Priority Select Encoding
PLS[4:0]
00000
00001–11110
11111
Priority Level
0 (lowest)
1–30
31 (highest)
Vector Number
00000
00001–11110
11111
7.8 Functional Description
The interrupt controller collects interrupt requests from multiple interrupt
sources and provides an interface to the processor core interrupt logic.
Interrupt controller functions include:
• Interrupt source prioritization
• Fast and normal interrupt requests
• Autovectored and vectored interrupt requests
• Interrupt configuration
MMC2107 – Rev. 2.0
MOTOROLA
Interrupt Controller Module
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Technical Data
167