MMC2107 Datasheet, PDF (326/618 Pages) –

Freescale Semiconductor, Inc.
Timer Modules (TIM1 and TIM2)
15.9 Reset
Reset initializes the timer registers to a known startup state as described
in the 15.7 Memory Map and Registers.
15.10 Interrupts
Table 15-8 lists the interrupt requests generated by the timer.
Table 15-8. Timer Interrupt Requests
Interrupt Request
Channel 3 IC/OC
Channel 2 IC/OC
Channel 1 IC/OC
Channel 0 IC/OC
PA overflow
PA input
Timer overflow
Flag
C3F
C2F
C1F
C0F
PAOVF
PAIF
TOF
Enable Bit
C3I
C2I
C1I
C0I
PAOVI
PAI
TOI
15.10.1 Timer Channel Interrupts (CxF)
A channel flag is set when an input capture or output compare event
occurs. Clear a channel flag by writing a 1 to it.
NOTE:
When the fast flag clear all bit, TFFCA, is set, an input capture read or
an output compare write clears the corresponding channel flag. TFFCA
is in timer system control register 1 (TIMSCR1).
When a channel flag is set, it does not inhibit subsequent output
compares or input captures
Technical Data
326
Timer Modules (TIM1 and TIM2)
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MMC2107 – Rev. 2.0
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