MMC2107 Datasheet, PDF (478/618 Pages) –

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
NOTE:
The guideline for selecting PSH and PSL is to maintain approximately
50 percent duty cycle; for prescaler values less than 16 or PSH ~=PSL.
For prescaler values greater than 16, keep PSL as large as possible.
Figure 18-42 shows that the prescaler is essentially a variable pulse
width signal generator. A 5-bit down counter, clocked at the system clock
rate, is used to create both the high phase and the low phase of the
QCLK signal. At the beginning of the high phase, the 5-bit counter is
loaded with the 5-bit PSH value. When the 0 detector finds that the high
phase is finished, the QCLK is reset. A 3-bit comparator looks for a one’s
complement match with the 3-bit PSL value, which is the end of the low
phase of the QCLK.
These equations define QCLK frequency:
high QCLK time = (PSH + 1) ÷ f_sys
low QCLK time = (PSL + 1) ÷ f_sys
f_QCLK = 1 ÷ (high QCLK time + low QCLK time)
Where:
PSH = 0 to 31, the prescaler QCLK high cycles in QACR0
PSL = 0 to 7, the prescaler QCLK low cycles in QACR0
f_sys = system clock frequency
f_QCLK = QCLK frequency
These are equations for calculating the QCLK high and low phases in
example 1:
high QCLK time = (11 + 1) ÷ 40 × 10⁶ = 300 ns
low QCLK time = (7 + 1) ÷ 40 × 10⁶ = 200 ns
f_QCLK = 1/(300 + 200) = 2 MHz
These are equations for calculating the QCLK high and low phases in
example 2:
high QCLK time = (7 + 1) ÷ 32 × 10⁶ = 250 ns
low QCLK time = (7 + 1) ÷ 32 × 10⁶ = 250 ns
f_QCLK = 1/(250 + 250) = 2 MHz
Technical Data
478
Queued Analog-to-Digital Converter (QADC)
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MMC2107 – Rev. 2.0
MOTOROLA