MMC2107 Datasheet, PDF (172/618 Pages) –

Freescale Semiconductor, Inc.
Interrupt Controller Module
7.8.4.3 Interrupt Source Configuration
Each module that is capable of generating an interrupt request has an
interrupt request enable/disable bit. To allow the interrupt source to be
asserted, set the local interrupt enable bit.
Once an interrupt request is asserted, the module keeps the source
asserted until the interrupt service routine performs a special sequence
to clear the interrupt flag. Clearing the flag negates the interrupt request.
7.8.5 Interrupts
The interrupt controller assigns a number to each interrupt source, as
Table 7-6 shows.
Table 7-6. Interrupt Source Assignment
Source Module Flag
Source Description
Flag Clearing Mechanism
0
PF1 Queue 1 conversion pause Write PF1 = 0 after reading PF1 = 1
1
CF1 Queue 1 conversion complete Write CF1 = 0 after reading CF1 = 1
ADC
2
PF2 Queue 2 conversion pause Write PF2 = 0 after reading PF2 = 1
3
CF2 Queue 2 conversion complete Write CF2 = 0 after reading CF2 = 1
4
MODF Mode fault
SPI
5
SPIF Transfer complete
Write to SPICR1 after reading MODF = 1
Access SPIDR after reading SPIF = 1
6
TDRE Transmit data register empty Write SCIDRL after reading TDRE = 1
7
TC Transmit complete
Write SCIDRL after reading TC = 1
8
SCI1 RDRF Receive data register full
Read SCIDRL after reading RDRF = 1
9
OR Receiver overrun
Read SCIDRL after reading OR = 1
10
IDLE Receiver line idle
Read SCIDRL after reading IDLE = 1
11
TDRE Transmit data register empty Write SCIDRL after reading TDRE = 1
12
TC Transmit complete
Write SCIDRL after reading TC = 1
13
SCI2 RDRF Receive data register full
Read SCIDRL after reading RDRF = 1
14
OR Receiver overrun
Read SCIDRL after reading OR = 1
15
IDLE Receiver line idle
Read SCIDRL after reading IDLE = 1
Technical Data
172
Interrupt Controller Module
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MMC2107 – Rev. 2.0
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