MMC2107 Datasheet, PDF (447/618 Pages) –

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Functional Description
PQA4
PQA0
PQB3
PQB0
V_RH
V_RL
V_DDA
V_SSA
4
CHAN. DECODE & MUX
8: 1
10-BIT A/D CONVERTER
INPUT
BIAS CIRCUIT
SAMPLE
BUFFER
10-BIT RC
DAC
CSAMP
ANALOG
POWER
COMPAR-
ATOR
INTERNAL
CHANNEL
DECODE
POWER
DOWN
STATE MACHINE & LOGIC
SAR TIMING
10
10
SUCCESSIVE
APPROXIMATION
REGISTER
CHAN[5:0]
STOP
RST
QCLK
2
IST
BYP
START CONV.
END OF CONV.
SAR[9:0]
Figure 18-19. QADC Analog Subsystem Block Diagram
Therefore, conversion time requires a minimum of 14 QCLK clocks (7 µs
with a 2.0-MHz QCLK). If the maximum final sample time period of 16
QCLKs is selected, the total conversion time is 28 QCLKs or 14 µs (with
a 2.0-MHz QCLK).
BUFFER
SAMPLE
TIME:
2 CYCLES
FINAL
SAMPLE
TIME:
N CYCLES
(2,4,8,16)
RESOLUTION
TIME:
10 CYCLES
QCLK
SAMPLE TIME
SUCCESSIVE APPROXIMATION RESOLUTION SEQUENCE
Figure 18-20. Conversion Timing
MMC2107 – Rev. 2.0
MOTOROLA
Queued Analog-to-Digital Converter (QADC)
For More Information On This Product,
Go to: www.freescale.com
Technical Data
447