MMC2107 Datasheet, PDF (555/618 Pages) –

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
Signal Descriptions
21.13 Signal Descriptions
The OnCE pin interface is used to transfer OnCE instructions and data
to the OnCE control block. Depending on the particular resource being
accessed, the CPU may need to be placed in debug mode. For
resources outside of the CPU block and contained in the OnCE block,
the processor is not disturbed and may continue execution. If a
processor resource is required, the OnCE controller may assert a debug
request (DBGRQ) to the CPU. This causes the CPU to finish the
instruction being executed, save the instruction pipeline information,
enter debug mode, and wait for further commands. Asserting DBGRQ
causes the device to exit stop, doze, or wait mode.
21.13.1 Debug Serial Input (TDI)
Data and commands are provided to the OnCE controller through the
TDI pin. Data is latched on the rising edge of the TCLK serial clock. Data
is shifted into the OnCE serial port least significant bit (LSB) first.
21.13.2 Debug Serial Clock (TCLK)
The TCLK pin supplies the serial clock to the OnCE control block. The
serial clock provides pulses required to shift data and commands into
and out of the OnCE serial port. (Data is clocked into the OnCE on the
rising edge and is clocked out of the OnCE serial port on the falling
edge.) The debug serial clock frequency must be no greater than
50 percent of the processor clock frequency.
21.13.3 Debug Serial Output (TDO)
Serial data is read from the OnCE block through the TDO pin. Data is
always shifted out the OnCE serial port LSB first. Data is clocked out of
the OnCE serial port on the falling edge of TCLK. TDO is three-stateable
and is actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCLK.
MMC2107 – Rev. 2.0
MOTOROLA
JTAG Test Access Port and OnCE
For More Information On This Product,
Go to: www.freescale.com
Technical Data
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