MMC2107 Datasheet, PDF (389/618 Pages) –

Freescale Semiconductor, Inc.
Serial Peripheral Interface Module (SPI)
Functional Description
After the 16th and final SCK edge:
• Data that was in the master SPIDR register is in the slave SPIDR.
Data that was in the slave SPIDR register is in the master SPIDR.
• The SCK clock stops and the SPIF flag in SPISR is set, indicating
that the transmission is complete. If the SPIE bit in SPCR1 is set,
SPIF generates an interrupt request.
Figure 17-11 shows the timing of a transmission with the CPHA bit set.
The SS pin of the master must be either high or configured as a
general-purpose output not affecting the SPI.
BEGIN TRANSMISSION
SCK (CPOL = 0)
END TRANSMISSION
SCK (CPOL = 1)
SAMPLE INPUT
MOSI/MISO
CHANGE OUTPUT
MOSI PIN
CHANGE OUTPUT
MISO PIN
SS PIN OUTPUT
MASTER ONLY
SLAVE SS PIN
t_L
MSB FIRST (LSBFE = 0):
MSB
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
LSB FIRST (LSBFE = 1):
LSB
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5
Legend:
t_L = Minimum leading time before the first SCK edge
t_T = Minimum trailing time after the last SCK edge
t_I = Minimum idling time between transmissions (minimum SS high time)
t_L, t_T, and t_I are guaranteed for master mode and required for slave mode.
BIT 1
BIT 6
t_T
LSB
MSB
t_I t_L
MINIMUM 1/2 SCK
FOR t_T, t_L, t_l
Figure 17-11. SPI Clock Format 1 (CPHA = 1)
MMC2107 – Rev. 2.0
MOTOROLA
Serial Peripheral Interface Module (SPI)
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Technical Data
389