MMC2107 Datasheet, PDF (556/618 Pages) –

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
21.13.4 Debug Mode Select (TMS)
The TMS input is used to cycle through states in the OnCE debug
controller. Toggling the TMS pin while clocking with TCLK controls the
transitions through the TAP state controller.
21.13.5 Test Reset (TRST)
The TRST input is used to reset the OnCE controller externally by
placing the OnCE control logic in a test logic reset state. OnCE operation
is disabled in the reset controller and reserved states.
21.13.6 Debug Event (DE)
The DE pin is a bidirectional open drain pin. As an input, DE provides a
fast means of entering debug mode from an external command
controller. As an output, this pin provides a fast means of acknowledging
debug mode entry to an external command controller.
The assertion of this pin by a command controller causes the CPU to
finish the current instruction being executed, save the instruction
pipeline information, enter debug mode, and wait for commands to be
entered from the TDI line. If DE was used to enter debug mode, then DE
must be negated after the OnCE responds with an acknowledgment and
before sending the first OnCE command.
The assertion of this pin by the CPU acknowledges that it has entered
debug mode and is waiting for commands to be entered from the TDI
line.
21.14 Functional Description
The on-chip emulation (OnCE) circuitry provides a simple, inexpensive
debugging interface that allows external access to the processor’s
internal registers and to memory/peripherals. OnCE capabilities are
controlled through a serial interface, mapped onto a JTAG test access
port (TAP) protocol. Figure 21-6 shows the components of the OnCE
circuitry.
Technical Data
556
JTAG Test Access Port and OnCE
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MMC2107 – Rev. 2.0
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