MMC2107 Datasheet, PDF (146/618 Pages) –

Freescale Semiconductor, Inc.
M•CORE M210 Central Processor Unit (CPU)
Arithmetic and logical operations are executed in a single cycle.
Multiplication is implemented with a 2-bit per clock, overlapped-scan,
modified Booth algorithm with early-out capability, to reduce execution
time for operations with small multipliers. Divide is implemented with a
1-bit per clock early-in algorithm. The find-first-one unit operates in a
single clock cycle.
The program counter unit incorporates a dedicated branch address
adder to minimize delays during change of flow operations. Branch
target addresses are calculated in parallel with branch instruction
decode. Taken branches and jumps require only two clocks; branches
which are not taken execute in a single clock.
Memory load and store operations are provided for 8-bit (byte), 16-bit
(half-word), and 32-bit (word) data, with automatic zero extension for
byte and half-word load operations. These instructions can execute in as
few as two clock cycles. Load and store multiple register instructions
allow low overhead context save and restore operations. These
instructions can execute in (N+1) clock cycles, where N is the number of
registers to transfer.
A condition code/carry (C) bit is provided for condition testing and for use
in implementing arithmetic and logical operations with operands/results
greater than 32 bits. The C bit is typically set by explicit test/comparison
operations, not as a side-effect of normal instruction operation.
Exceptions to this rule occur for specialized operations where it is
desirable to combine condition setting with actual computation.
The processor uses autovectors for both normal and fast interrupt
requests. Fast interrupts take precedence over normal interrupts. Both
types have dedicated exception shadow registers. For service requests
of either kind, an automatic vector is generated when the request is
made.
Technical Data
146
M•CORE M210 Central Processor Unit (CPU)
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MMC2107 – Rev. 2.0
MOTOROLA