MMC2107 Datasheet, PDF (236/618 Pages) –

Clock Module
Freescale Semiconductor, Inc.
10.8.2 System Clocks Generation
In normal PLL clock mode, the default system frequency is two times the
reference frequency after reset. The RFD[2:0] and MFD[2:0] bits in
SYNCR select the frequency multiplier.
When programming the PLL, do not exceed the maximum system clock
frequency listed in the electrical specifications. Use this procedure to
accommodate the frequency overshoot that occurs when the MFD bits
are changed:
1. Determine the appropriate value for the MFD and RFD fields in
SYNCR. The amount of jitter in the system clocks can be
minimized by selecting the maximum MFD factor that can be
paired with an RFD factor to provide the required frequency.
2. Write a value of RFD (from step 1) + 1 to the RFD field of SYNCR.
3. Write the MFD value from step 1 to SYNCR.
4. Monitor the LOCK flag in SYNSR. When the PLL achieves lock,
write the RFD value from step 1 to the RFD field of SYNCR. This
changes the system clocks frequency to the required frequency.
NOTE: Keep the maximum system clock frequency below the limit given in
Section 22. Electrical Specifications.
10.8.3 PLL Lock Detection
The lock detect logic monitors the reference frequency and the PLL
feedback frequency to determine when frequency lock is achieved.
Phase lock is inferred by the frequency relationship, but is not
guaranteed. The LOCK flag in SYNSR reflects the PLL lock status. A
sticky lock flag, LOCKS, is also provided.
The lock detect function uses two counters. One is clocked by the
reference and the other is clocked by the PLL feedback. When the
reference counter has counted N cycles, its count is compared to that of
the feedback counter. If the feedback counter has also counted N cycles,
the process is repeated for N + K counts. Then, if the two counters still
match, the lock criteria is relaxed by 1/2 and the system is notified that
the PLL has achieved frequency lock.
Technical Data
236
Clock Module
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MMC2107 – Rev. 2.0
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