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MMC2107 Datasheet, PDF (488/618 Pages) – | |||
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Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
3FF
3FE
3FD
3FC
3FB
3FA
8
7
6
5
4
3
2
1
0
.010
.020
.030
5.100 5.110
5.120 5.130
INPUTS IN VOLTS (VRH = 5.120 V, VRL = 0 V)
Figure 18-46. Errors Resulting from Clipping
18.11.3 Conversion Timing Schemes
This section contains some conversion timing examples. Figure 18-47
shows the timing for basic conversions where it is assumed that:
⢠Q1 begins with CCW0 and ends with CCW3.
⢠CCW0 has pause bit set.
⢠CCW1 does not have pause bit set.
⢠External trigger rise edge for Q1.
⢠CCW4 = BQ2 and Q2 is disabled.
⢠Q1 Res shows relative result register updates.
Recall that when QS = 0, both queues are disabled, when QS = 8,
queue 1 is active and queue 2 is idle, and when QS = 4, queue 1 is
paused and queue 2 is disabled.
Technical Data
488
Queued Analog-to-Digital Converter (QADC)
For More Information On This Product,
Go to: www.freescale.com
MMC2107 â Rev. 2.0
MOTOROLA
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