MMC2107 Datasheet, PDF (304/618 Pages) –

Freescale Semiconductor, Inc.
Timer Modules (TIM1 and TIM2)
15.7.5 Timer Counter Registers
Address: TIM1 — 0x00ce_0004
TIM2 — 0x00cf_0004
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset: 0
0
0
0
0
0
0
0
= Writes have no effect and the access terminates without a transfer error exception.
Figure 15-6. Timer Counter Register High (TIMCNTH)
Address: TIM1 — 0x00ce_0005
TIM2 — 0x00cf_0005
Bit 7
6
5
4
3
2
1
Bit 0
Read: Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset: 0
0
0
0
0
0
0
0
= Writes have no effect and the access terminates without a transfer error exception.
Figure 15-7. Timer Counter Register Low (TIMCNTL)
Read: Anytime
Write: Only in test (special) mode; has no effect in normal modes
To ensure coherent reading of the timer counter, such that a timer
rollover does not occur between two back-to-back 8-bit reads, it is
recommended that only half-word (16-bit) accesses be used.
A write to TIMCNT may have an extra cycle on the first count because
the write is not synchronized with the prescaler clock. The write occurs
at least one cycle before the synchronization of the prescaler clock.
Technical Data
304
Timer Modules (TIM1 and TIM2)
For More Information On This Product,
Go to: www.freescale.com
MMC2107 – Rev. 2.0
MOTOROLA