MMC2107 Datasheet, PDF (342/618 Pages) –

Freescale Semiconductor, Inc.
Serial Communications Interface Modules (SCI1 and SCI2)
16.7.4 SCI Status Register 1
Address: SCI1 — 0x00cc_0004
SCI2 — 0x00cd_0004
Bit 7
6
5
4
3
2
1
Bit 0
Read: TDRE
TC
RDRF IDLE
OR
NF
FE
PF
Write:
Reset: 1
1
0
0
0
0
0
0
= Writes have no effect and the access terminates without a transfer error exception.
Figure 16-6. SCI Status Register 1 (SCISR1)
Read: Anytime
Write: Has no meaning or effect
TDRE — Transmit Data Register Empty Flag
The TDRE flag is set when the transmit shift register receives a word
from the SCI data register. It signals that the SCIDRH and SCIDRL
are empty and can receive new data to transmit. If the TIE bit in the
SCICR2 is also set, TDRE generates an interrupt request. Clear
TDRE by reading SCISR1 and then writing to SCIDRL. Reset sets
TDRE.
1 = Transmit data register empty
0 = Transmit data register not empty
TC — Transmit Complete Flag
The TC flag is set when TDRE = 1 and no data, preamble, or break
frame is being transmitted. It signals that no transmission is in
progress. If the TCIE bit is set in SCICR2, TC generates an interrupt
request. When TC is set, the TXD pin is idle (logic 1). TC is cleared
automatically when a data, preamble, or break frame is queued. Clear
TC by reading SCISR1 with TC set and then writing to SCIDRL. TC
cannot be cleared while a transmission is in progress. Reset sets TC.
1 = No transmission in progress
0 = Transmission in progress
Technical Data
342
Serial Communications Interface Modules (SCI1 and SCI2)
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MMC2107 – Rev. 2.0
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