MMC2107 Datasheet, PDF (562/618 Pages) –

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
Bit 7
6
5
4
3
2
1
Bit 0
R/W
G
EX
RS4
RS3
RS2
RS1
RS0
Figure 21-8. OnCE Command Register (OCMR)
R/W — Read/Write Bit
1 = Read the data in the register specified by the RS field.
0 = Write the data associated with the command into the register
specified by the RS field.
GO — Go Bit
When the GO bit is set, the device executes the instruction in the IR
register in the CPUSCR. To execute the instruction, the processor
leaves debug mode, executes the instruction, and if the EX bit is
cleared, returns to debug mode immediately after executing the
instruction. The processor resumes normal operation if the EX bit is
set. The GO command is executed only if the operation is a read/write
to either the CPUSCR or to “no register selected.” Otherwise, the GO
bit has no effect. The processor leaves debug mode after the TAP
controller update-DR state is entered.
1 = Execute instruction in IR
0 = Inactive (no action taken)
EX — Exit Bit
When the EX bit is set, the processor leaves debug mode and
resumes normal operation until another debug request is generated.
The exit command is executed only if the GO bit is set and the
operation is a read/write to the CPUSCR or a read/write to “no register
selected.” Otherwise, the EX bit has no effect. The processor exits
debug mode after the TAP controller update-DR state is entered.
1 = Leave debug mode
0 = Remain in debug mode
RS4–RS0 — Register Select Field
The RS field defines the source for the read operation or the
destination for the write operation. Table 21-4 shows OnCE register
addresses.
Technical Data
562
JTAG Test Access Port and OnCE
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MMC2107 – Rev. 2.0
MOTOROLA